Single Pass Connected Components Analysis

Abstract

The classic connected components labelling algorithm requires a minimum of 2 passes through an image. This paper presents a modification of this algorithm that allows the resolution of merged labels to be deferred. This enables the subsequent data analysis step to be combined with the labelling procedure, with the result that connected components can be analysed in a single pass by gathering data on the regions as they are built. This avoids the need for buffering the image, making the algorithm ideally suited for processing streamed images on an FPGA or other embedded system with limited memory. It is shown that an FPGA-based design could use 1 clock cycle per pixel with a small overhead to manage merging of “U ” shaped components. It is demonstrated that the worst case overhead is 20 % of the image, although for typical images the overhead is less than 1%.

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